Constructing of an electronic assembly having a decoupling capacitor

ABSTRACT

An electronic assembly is provided, having a capacitor interconnected between BGA solder balls. The capacitor is placed on a motherboard and soldered to the BGA solder balls when the BGA solder balls are soldered to electric lands on the motherboard.

BACKGROUND OF THE INVENTION

1). Field of the Invention

This invention relates to an electronic assembly having a decouplingcapacitor and to a method according to which it is constructed.

2). Discussion of Related Art

Integrated circuits are usually manufactured in and on semiconductorwafers that are subsequently diced or singulated into individualmicroelectronic dies. Such a microelectronic die is usually mounted to apackage substrate for purposes of providing rigidity thereto and throughwhich signals can be provided to and from the integrated circuit. Such apackage substrate often has an array of solder ball interconnectionmembers, also referred to as a ball grid array (BGA), on an opposingsurface that are placed on electric lands of a motherboard and, by athermal reflow process, soldered thereto.

Such a motherboard usually includes a carrier substrate with a powerplane and a ground plane therein. A power source is connected to thepower plane, and the ground plane is connected to ground. The power andground planes are connected to separate ones of the electric lands. Inaddition, input and output (IO) signal sources are connected to otherones of the electric lands. Power, ground, and IO signals can thus beprovided through the motherboard, the solder ball interconnectionmembers, and the package substrate to and from the integrated circuit inthe microelectronic die.

In order to reduce inductive-capacitance delay, it is usuallyadvantageous to include one or more decoupling capacitors havingopposing terminals connected to the power and ground planes. An existingtechnique is to connect a capacitor between two of the solder ballinterconnection members before the solder ball interconnection membersare located on the electric lands of the motherboard. Such a process isexpensive because it requires additional manufacturing steps, includingthe placement of the capacitor, and controlled heating and cooling ofthe solder ball interconnection members so that they reflow overcapacitor terminals of the capacitor. These steps have to be carried outbefore the package (i.e., the combination of the package substrate, themicroelectronic die, the solder ball interconnection members, and thecapacitor) are shipped to an entity that does the final assembly on themotherboard.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described by way of example with reference to theaccompanying drawings, wherein:

FIG. 1 is a cross-sectional side view illustrating an electronicassembly, according to an embodiment of the invention, having adecoupling capacitor between a semiconductor package and a motherboardof the assembly;

FIG. 2A is a cross-sectional side view illustrating a portion of thesemiconductor package and a portion of the motherboard after thecapacitor is located on the motherboard;

FIG. 2B is a view similar to FIG. 2A after the semiconductor package ispositioned on the motherboard;

FIG. 2C is a view similar to FIG. 2B after reflow of solder ballinterconnection members of the semiconductor package;

FIG. 3 is a top plan view illustrating a layout of electric lands, andpower and ground planes of the motherboard; and

FIG. 4 is a top plan view illustrating more ground and power planes thatare interconnected with additional decoupling capacitors.

DETAILED DESCRIPTION OF THE INVENTION

An electronic assembly is provided, having a capacitor interconnectedbetween BGA solder balls. The capacitor is placed on a motherboard andsoldered to the BGA solder balls when the BGA solder balls are solderedto electric lands on the motherboard.

FIG. 1 of the accompanying drawings illustrates an electronic assembly 8according to an embodiment of the invention. The electronic assembly 8includes a motherboard 10, a semiconductor package 12, and a capacitor14 mounted to the motherboard 10.

The motherboard 10 includes a carrier substrate 16 which is made of anonconductive dielectric material. The motherboard 10 further has aplurality of electric lands 18 that are formed near an upper surface ofthe carrier substrate 16. The motherboard 10 further has power andground planes 20 and 22 respectively. The electric lands 18 and thepower and ground planes 20 and 22 are at the same elevation and areformed below an upper surface of a solder mask or upper dielectric layer24 of the carrier substrate 16. Openings are formed in the upperdielectric layer 24 through which portions of the power and groundplanes 20 and 24 are also exposed to leave additional electric lands 18on the power and ground planes 20 and 24 exposed. Metal lines 26 areformed in the carrier substrate 16. Some of the metal lines 26 connectsome of the electric lands 18 to input and output (IO) signals 28. Oneof the lines 26 connects the power plane 20 to a power source 30.Another one of the lines 26 connects the ground plane 22 to ground 32.

The semiconductor package 12 includes a package substrate 36, amicroelectronic die 38, a plurality of contact pads 40, and a pluralityof solder ball interconnection members 42.

The microelectronic die 38 is typically a semiconductor die having anintegrated circuit formed therein. The microelectronic die 38 is mountedon an upper surface of the package substrate 36. A plurality ofcontrolled collapse chip connect (C4) interconnection members 42 areformed in an array on a lower surface of the microelectronic die 38, andare used to connect the microelectronic die 38 structurally andelectrically to terminals on the package substrate 36. The contact pads40 are formed on a lower surface of the package substrate 36. Metallines 44 in the package substrate 36 interconnect the terminals on theupper surface thereof with the contact pads 40. Each solder ballinterconnection member 42 is attached to a respective one of the contactpads 40, typically before the microelectronic die 38 is mounted on thepackage substrate 36.

FIGS. 2A, 2B, and 2C illustrate how the solder ball interconnectionmembers 42 are attached to the electric lands 18. FIGS. 2A, 2B, and 2Calso illustrate how the capacitor 14 is connected between two of thesolder ball interconnection members 42 and through the solder ballinterconnection members 42 to the power and ground planes 20 and 22shown in FIG. 1.

As illustrated in FIG. 2A, a layer of solder paste 46 is first appliedto each electric land 18. The capacitor 14 has a capacitor body 48 andcapacitor terminals 50 and 52 at each respective end of the capacitorbody 48. The capacitor 14 is positioned above the carrier substrate 16with each capacitor terminal 50 or 52 resting on a respective one of theelectric lands 18. The layers of solder paste 46 provide a tackinessthat retains the capacitor terminals 50 and 52 in position. What can benoted is that the capacitor 14 is not permanently attached to theelectric lands 18 or the solder ball interconnection members 42 at thisstage, and that the package substrate 36 and solder ball interconnectionmembers 42 are still distant from the capacitor 14 and the electriclands 18.

Next, as illustrated in FIG. 2B, the package substrate 36 (with themicroelectronic die 38 thereon) is lowered down to the motherboard 10until each one of the solder ball interconnection members 42 insertsitself into a respective layer of solder paste 46. The arrangement ofthe solder ball interconnection members 42 thus matches the layout ofthe electric lands 18. The solder ball interconnection members 42 are atall stages still solid (not softened or melted), and the capacitorterminals 52 fit in between two of the solder ball interconnectionmembers 42A and 42B. The capacitor 14 is now between the packagesubstrate 36 and the motherboard 10, and covered by the packagesubstrate 36.

FIG. 2C illustrates the assembly of FIG. 2B after the entire assembly isheated and subsequently allowed to cool. Heating softens, melts, andreflows the solder ball interconnection members 42, and the reflow isassisted by the layers of solder paste 46. Each solder ballinterconnection member 42 reflows onto the respective electric land 18on which it is located and, after cooling down and again solidifying, isstructurally and electrically connected to the respective electric land18. The package substrate 36 is now mounted at a spaced location aboveand to the motherboard 10. In addition, the solder ball interconnectionmembers 42A and 42B reflow onto upper end and side surfaces of thecapacitor terminals 50 and 52 respectively. After being cooled down, thecapacitor terminal 50 is connected through the solder ballinterconnection member 42A to the electric land 18 to which the solderball interconnection member 42A is attached. Similarly, the capacitorterminal 52 is connected through the solder ball interconnection member42B to the electric land 18 to which it is attached.

Referring again to FIG. 1, it can be seen that the capacitor 14 connectsthe power and ground planes 20 and 22 to one another, to reduceresistive-capacitive delay. An advantage of having the capacitor 14between the motherboard 10 and the semiconductor package 12 is thatdecoupling capacitance can be provided closer to the semiconductorpackage 12, and to the microelectronic die 38.

The manner in which the electronic assembly 8 is assembled is that thecapacitor 14 does not have to be pre-mounted to the semiconductorpackage 12 at great cost. A subcontractor may, accordingly, simplylocate the capacitor 14 on the motherboard 10 and connect the capacitor14 during normal BGA reflow.

FIG. 3 illustrates the layout of the electric lands 18 in order toaccommodate the capacitor 14. Three of the electric lands 18A, 18B, and18C are in a first row. Two more of the electric lands 18D and 18E arein a second row parallel to the first row. Two more of the electriclands 18F and 18G are in a third row parallel to the second row, withthe second row between the first and third rows.

The electric land 18A is in a first column, and portions of the electriclands 18D and 18F are in the same column as the electric land 18A.Similarly, the electric land 18C is in a second column, and portions ofthe electric lands 18E and 18G are in the second column of the electricland 18C. The electric land 18B is in a third column between the firstand second columns. There is no electric land in the second row (whichincludes the electric lands 18D and 18E) having a center point in thethird column of the electric land 18B. Similarly, there is no electricland in the third row (of the electric lands 18F and 18G) having acenter point in the second column of the electric land 18B. The secondand third rows are thus “depopulated” when compared with the first row.

The electric lands 18A, 18D, and 18F are all connected to the powerplane 20. The electric lands 18C, 18D, and 18G are all connected to theground plane 22. The power and ground planes 20 and 22 have a gapbetween them which is larger in the first row (of the electric lands18A, 18B, and 18C) than in the second and third rows (of the electriclands 18D, 18E, 18F, and 18G). The extra width of the spacing betweenthe power and ground planes 20 and 22 at the first row allows forplacement of the electric land 18B without being connected to either thepower or ground plane 20 or 22. Depopulation of the third column of theelectric land 18B at the second and third rows simultaneously allows forplacement of the capacitor 14 across the third column of the electricland 18B. Although the capacitor illustrated in FIG. 3 is relativelyshort, a larger capacitor can be used because such a larger capacitorwould be connected to electric lands 18F and 18G in columns that arerelatively far apart.

As illustrated in FIG. 4, multiple power or ground planes may beprovided, in the present example one power plane 20 and two groundplanes 22A and 22B. The power and ground planes 20, 22A, and 22B can beinterconnected with multiple capacitors 14A, 14B, and 14C. The powerplane 20 can also be connected to the ground plane 22A with twocapacitors 14A and 14B. The design thus allows for placement ofcapacitors according to the requirements for decoupling capacitors in aparticular area.

The capacitor terminals 50 and 50A are each located on a respective oneof the electric lands 18.

While certain exemplary embodiments have been described and shown in theaccompanying drawings, it is to be understood that such embodiments aremerely illustrative and not restrictive of the current invention, andthat this invention is not restricted to the specific constructions andarrangements shown and described since modifications may occur to thoseordinarily skilled in the art.

1-16. (canceled)
 17. A method of constructing an electronic assembly,comprising: positioning a capacitor on a first substrate; positioning asecond substrate adjacent the first substrate with solid interconnectionmembers between respective electric lands on the first substrate andrespective contact pads on the second substrate and with the capacitorbetween the substrates; heating the interconnection members to reflowthe interconnection members, two of the interconnection membersreflowing onto terminals of the capacitor located between thesubstrates; and allowing the interconnection members to cool andsolidify.
 18. The method of claim 17, wherein the capacitor is notattached through the interconnection members to either substrate whenthe second substrate is positioned adjacent the first substrate.
 19. Themethod of claim 17, wherein the capacitor and the interconnectionmembers are on the first substrate before the second substrate islocated on the first substrate, and wherein a microelectronic die ismounted to the second substrate.
 20. A method of constructing anelectronic assembly, comprising: attaching solder ball interconnectionmembers to contact pads on a package substrate; mounting amicroelectronic die to the package substrate; locating a capacitor on acarrier substrate; positioning the package substrate above the carriersubstrate, with each solder ball interconnection member on a respectiveone of a plurality of electric lands on the carrier substrate, and thepackage substrate covering the capacitor; heating the solder ballinterconnection members so that at least some of the solder ballinterconnection members reflow onto the electric lands, and at leastfirst and second ones of the solder ball interconnection members reflowonto first and second capacitor terminals, respectively, of thecapacitor; and allowing the solder ball interconnection members to cooland solidify.
 21. The method of claim 20, wherein the first solder ballinterconnection member is connected to a ground plane carried by thecarrier substrate, and the second solder ball interconnection member isconnected to a power plane carried by the carrier substrate.
 22. Themethod of claim 20, further comprising: applying solder paste to theelectric lands, the first and second terminals of the capacitor beinglocated on the solder paste.